1. Field of the Invention
The present invention relates to a semiconductor memory device which uses a resistive memory element as a memory cell and writes information by using an electric current flowing through the resistive memory element and, more particularly, to a semiconductor memory device in which a memory cell unit comprises two transistors and three resistive memory elements, and data write and read methods of the same.
2. Description of the Related Art
Recently, semiconductor memories such as a PRAM (Phase change Random Access Memory) and MRAM (Magnetoresistive Random Access Memory) using resistive elements as memory elements are attracting attention and developed. The former is a semiconductor memory that stores information by changing the resistance value of a resistive memory element by changing the phase of the crystal structure of the element by supplying a write current to it. The latter is a semiconductor memory that uses, as a memory element, a magnetoresistive element having a structure called an MTJ (Magnetic Tunnel Junction) in which two ferromagnetic materials sandwich an insulating film, the magnetization direction in one ferromagnetic layer (a fixed layer) is fixed, and the magnetization direction in the other ferromagnetic layer (a recording layer) is reversible. This semiconductor memory stores information by using a so-called magnetoresistive effect by which the resistance value changes in accordance with relative magnetization directions in the recording layer and fixed layer. In particular, the MRAM has the characteristics that it is nonvolatile, can operate at a high speed, can be highly integrated, and has high reliability. Therefore, the MRAM is expected and developed as a memory device capable of replacing the SRAM, PSRAM (Pseudo SRAM), DRAM, and the like.
Conventionally, a so-called current-induced magnetic field write method that reverses the magnetization direction in the recording layer by a magnetic field induced by an electric current flowing through a write line is the general write method of the MRAM. On the other hand, a so-called spin injection MRAM using magnetization reversal caused by polarized spin current injection is recently attracting attention (e.g., patent reference 1 and non-patent reference 1). In this method, the density of an electric current flowing through a magnetoresistive element defines a current amount (reversing threshold current) necessary for spin injection magnetization reversal. Accordingly, the reversing threshold current amount reduces as the area of the magnetoresistive element reduces. That is, the method is expected as a technique capable of implementing a gigabit-class MRAM since the reversing threshold current is also scaled.
The write operation of the spin injection MRAM is performed by supplying a write current equal to or larger than the reversing threshold current to the magnetoresistive element, and the direction of the write current flowing through the magnetoresistive element determines the polarity of data to be written. The read operation is performed by reading out the bit line potential by supplying a constant electric current to the magnetoresistive element, or reading out an electric current flowing through the magnetoresistive element by applying a constant voltage, as in the conventional current-induced magnetic field write type MRAM. That is, a memory cell of the spin injection MRAM requires no write word line that is necessary in the conventional current-induced magnetic field write type MRAM. In a general 1Tr+1MTJ memory cell, for example, one terminal of the MTJ element is connected to a first bit line, the other terminal of the MTJ element is connected to one source/drain electrode of a transistor, the other source/drain electrode of the transistor is connected to a second bit line, and the gate electrode of the transistor is connected to a word line. In this case, the memory cell size is 8F2 (F is a minimum feature size).
On the other hand, a RAM that is presently most widely used is a DRAM. In order for the MRAM to replace this DRAM, the chip fabrication cost, i.e., the chip area of the MRAM must be equal to or smaller than that of the DRAM (the cell size of a general DRAM is 8F2). Generally, decreasing the cell size of a memory cell accounting for a high ratio in the chip area of a semiconductor memory is most effective to decrease the chip size of the semiconductor memory. To implement a low-cost spin injection MRAM, therefore, the cell size must be made smaller than that (8F2) of the DRAM. However, the cell size of the conventional spin injection MRAM is 8F2, i.e., equal to that of the DRAM as described above.
[Patent Reference 1] U.S. Pat. No. 5,695,864
[Non-patent Reference 1] 2005 IEDM Technical Digest, pp. 459-462, December 2005